1. Field of the Invention
The present invention relates generally to the architecture of memory cells in the integrated circuit (IC), and more particularly, to a memory circuit properly workable under low working voltage.
2. Description of the Related Art
The area and power of the static random access memory (SRAM) are key challenges for very large scale IC or system on chip; if the area is smaller, the cost of the chip can be reduced more effectively and the reliability of the memory circuit can be enhanced. Besides, the low-voltage operation has become one of the trends of the current low-power IC design, so the design of SRAM also needs to be developed toward low voltage and should take noise immunocompetence into account.
Among the rough classifications of SRAM cells, the conventional six-transistor (6T) cell is the most typical example. Thereafter, the SRAM cell was developed to be 7T cell, 8T cell, and 10T cell to properly work under low working voltage. The greatest advantage of the conventional 6T cell lies in its smallest area and lowest cost, compared with the 6T, 7T, and 8T cells, but the noise immunocompetence of the 6T cell is much worse than those of the 6T, 7T, and 8T cells.
FIG. 5 illustrates the conventional 6T cell structure. FIG. 6 illustrates the bit line architecture of the 6T cell. When read proceeds, the node n2 results in little rise of voltage level, because of voltage division, to lower static noise margin (SNM), so the saved value is subject to influence of external noises. When the noises exceed the SNM, the saved value will be damaged. Such circumstance will become worse while the operation proceeds under low voltage.
The design of the memory further needs to consider leakage current. When read proceeds, the logic of the word line WL is 1 and the bit line BL is connected with many memory inactive cells to be subject to the influence of the leakage current I_leak generated by the transistors 116 and 126. Besides, the whole leakage current may be great enough to lower the voltage level of the bit line BL down to 0 to further result in incorrect reading.
FIG. 7 illustrates a 7T-cell architecture proposed by Takeda, K., Hagihara, Y., Aimoto, Y., Nomura, M., Nakazawa, Y., Ishii, T., and Kobatake, H. on SOLID-STATE CIRCUITS, 2005 IEEE International Conference Digest of Technical Papers, in 2005 and disclosed in a dissertation titled “A read-static-noise-margin-free ASRAM cell for low-VDD and high-speed applications”. Compared with the 6T-cell architecture, the 7T-cell architecture includes one more transistor; its control line is composed of a write word line WWL, a read/write line WL, and a read/write inverted word line WLn and its data line is composed of a read/write bit line BL and a write bit line WBL.
The aforesaid 7T-cell architecture actually fails to work under too low voltage. When accumulation of leakage current or noise interference happens, the potential of the node q2 may rise. If the potential of the node q2 rises due to the leakage current of the PMOS (p-type metal oxide semiconductor) transistor 201, as the read time is longer, the rising potential of the node q2 will be higher. When the rising of the potential of the node q2 is too high, the potential of the nodes of the memory cells becomes inverted to change the node q2 from its logic “1” to “0” and change the node q1 from its logic “0” to “1” to further result in data error. Such phenomenon is called destructive read. When the working voltage is too low, the voltage tolerance becomes lower, so such phenomenon becomes more and more serious.
In addition, when the aforesaid 7T cells is writing, if the write noise margin is insufficient, write failure may happen. This problem becomes more serious as the working voltage is lower.
FIG. 8 illustrates that a bit-line architecture constituted based on 7T cells, which is still vulnerable to leakage current to result in read error. Similarly, when the working voltage is lower, this problem becomes more serious.
To enable the memory cells to work under lower working voltage stably and reliably, someone developed a more complicated architecture. FIG. 9 shows an 8T-cell architecture proposed by L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch at pages 128-129 of in Symp. VLSI Technology Dig. Tech. Papers in 2005 and disclosed in a dissertation titled “Stable SRAM Cell Design for the 32 nm Node and Beyond”. The emphases of this design lie in that read and write ends are separated and two additional NMOS (n-type metal oxide semiconductor) transistors function as an independent read end to avoid the aforesaid destructive read. FIG. 10 shows a 10T-cell architecture proposed by Calhoun, B. H.; Chandrakasan, A. at pages 2592-2601 of SOLID-STATE CIRCUITS, 2006 IEEE International Conference Digest of Technical Papers in 2006 and disclosed in an dissertation titled “A 256 kb Sub-threshold SRAM in 65 nm CMOS”. The emphases of this design lie in that read and write ends are also separated and to prevent the data line from suffering the leakage current under low voltage, the independent read end can further effectively control the leakage current of the cells toward the data line by means of a PMOS and three NMOS transistors. FIG. 11 shows a single-end six-transistor (S6T) memory cell architecture composed of a transmission gating 330 and a 4T latch formed of two inverters 331 and 332 as proposed by Bo Zhai; Blaauw, D., Sylvester, D., and Hanson, S. at pages 332-334 of SOLID-STATE CIRCUITS, 2007 IEEE International Conference Digest of Technical Papers in 2007 and disclosed in a dissertation titled “A Sub-200 mV 6T SRAM in 0.13 um CMOS”. The emphasis of this design is to prevent the conventional 6T cells from interference with two data lines in the process of read to further prevent the read noise immunocompetence of the cells from attenuation, making the single-end transmission gating be the read end for correctly transmitting cell storage voltage to the bit line. However, such design needs correct size of transistor to do the expected action.
Besides, one of the tendencies of the memory design is to reduce power consumption for controlling the way of power supply by means of power gating and for controlling current flowing back to the ground wire by means of ground gating. Recently, some improved designs of power gating and ground gating coordinated with the method of changing memory cells to more effectively save the power consumption or to make the circuit work more stably under low working voltage.
FIG. 12 shows a structure of the conventional 6T cell array to which power granting is applied as proposed by K. Zhang et al. at pages 474-475 of in IEEE Int. Solid-State Circuits Conf (ISSCC) Dig. Tech. Papers in 2005 and disclosed in a dissertation titled “A 3-GHz70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply”. In this structure, a big memory cell array is partitioned into many small memory cell banks. Each of the small memory cell banks includes two voltage sources, one of which is high-potential voltage source VDDH and the other is low-potential voltage source VDDL. Which of the voltage sources supplies voltage for the small memory cell banks is decided by PMOS power switch. Taking the power switches 410 and 411 as an example, in the time frame that the small memory cell banks are not working, activate the power switch 410 to deactivate the power switch 411 to connect the small memory cell banks to the power source VDDL for the purpose of lowering the power consumption of cell leakage current; in the time frame that the small memory cell banks are working, activate the power switch 411 to deactivate the power switch 410 to connect the small memory cell banks to the power source VDDH for the purpose of heightening power supply to accelerate the operation speed of the memory.
FIG. 13 shows a structure of the conventional 6T memory cell bank to which ground gating is applied as proposed by Yamaoka, M. and Shinozaki, Y. on SOLID-STATE CIRCUITS, 2004 IEEE International Conference Digest of Technical Papers in 2004 and disclosed in a dissertation titled “A 300-MHz 25 μA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor”. In this structure, a big memory cell array is likewise partitioned into many small memory cell banks. Each of the small memory cell banks is connected to a ground wire via an NMOS, a ground switch 421, an NMOS diode 422, and an NMOS resistor 423. An internal ground wire connected with the common drain of the ground switch 421, the NMOS diode 422, and the NMOS resistor 423 is defined as a virtual ground wire 42. In light of such structure, the consumption of leakage current of the cells can be reduced and the memory write-in ability can be strengthened.
FIG. 14 shows a structure of the memory cell bank to which a PMOS power switch is applied as derived from same literature indicated in FIG. 10. This structure is fully composed of 10T memory cells for the purpose of strengthening the rewrite and storage ability of the cells.
FIG. 15 shows a structure, in which a buffer functions as a read end of each array of the memory cell bank and each of the memory cell banks is composed of 8T memory cells, as proposed by Verna, N. and Chandrakasan, A. at pages 141-149, VOL. 43 of IEEE J. of Solid-State Circuit and disclosed in a dissertation titled “A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundance”. This structure can avoid affecting the read speed of the memory and prevent the cells from causing interference of leakage current with the bit line.
FIG. 16 shows a structure, in which improved power gating and improved ground gating are applied to each of the memory cell arrays, as derived from same literature as in FIG. 11. The memory cells in each array is composed of S6T memory cells and provided with a virtual power cord and a virtual ground wire. This structure can avoid affecting the read speed of the memory and strengthen the memory write-in ability.
To sum up, how to lower working voltage as disclosed in each of the aforesaid literatures basically includes two designs, one of which is changing the structure of the cells, like 6T-cell, 7T-cell, 8T-cell or 10T-cell structure and the other is combining control of power line or ground wire with the 6T-cell, 7T-cell, 8T-cell or 10T-cell structure for working together. However, applying the new cell structure can bring forth considerable increase of area of the memory bank, e.g. changing 6T-cell structure to 8T-cell structure as indicated in FIG. 9 consumes additional 30-40% area at least; as indicated in FIG. 15, changing 6T-cell structure to S6T-cell structure consumes additional 100% area. So far, none of any people has proposed preferred structure to save the area of the cells and meanwhile effectively lower the working voltage.